Top-down electroless chemical etching enables non-lithographic patterning of wafer-scale nanostructured arrays, but the etching on highly doped wafers produces porous structures. The lack of defect-free nanostructures at desired doping and the difficulties in forming reliable electrical side-contacts to the nanostructure arrays limits their integration into high performance nanoelectronics. We developed a barrier layer diffusion technique to controllably dope wafer-scale silicon nanowire arrays (10 17 –10 20 cm −3 ) produced by chemically etching lightly doped silicon wafers. In order to achieve low resistance top-side electrical contacts to the arrays, we developed a two step tip-doping procedure to locally dope the tips (∼10 20 cm −3 ) to metallic levels. The dopant concentration is characterized by depth profiling using secondary ion mass spectroscopy and four-point probe electrical measurements. Further, array scale electrical me...
Jyothi S Sadhu, Hongxiang Tian, Timothy Spila, Junhwan Kim, Bruno Azeredo, Placid Ferreira and Sanjiv Sinha
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Jyothi S Sadhu, Hongxiang Tian, Timothy Spila, Junhwan Kim, Bruno Azeredo, Placid Ferreira and Sanjiv Sinha
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