Nanoscale , 2014, Advance Article
DOI: 10.1039/C3NR06904D, Paper
DOI: 10.1039/C3NR06904D, Paper
Hongming Lv, Huaqiang Wu, Jinbiao Liu, Can Huang, Junfeng Li, Jiahan Yu, Jiebin Niu, Qiuxia Xu, Zhiping Yu, He Qian
CMOS compatible 200 mm two-layer-routing technology is employed to fabricate graphene field-effect transistors and monolithic graphene ICs.
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CMOS compatible 200 mm two-layer-routing technology is employed to fabricate graphene field-effect transistors and monolithic graphene ICs.
To cite this article before page numbers are assigned, use the DOI form of citation above.
The content of this RSS Feed (c) The Royal Society of Chemistry
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